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september 1998 1/89 this is preliminary information on a new product in development or undergoing evaluation. details are subject tochange without notice. ST72121 8-bit mcu with 8 to 16k rom/otp/eprom, 384 to 512 bytes ram, wdg, sci, spi and 2 timers preliminary data n user program memory (rom/otp/eprom): 8 to 16k bytes n data ram: 384 to 512 bytes including 256 bytes of stack n master reset and power-on reset n low voltage detector (lvd) reset option n run and power saving modes n 32 multifunctional bidirectional i/o lines: 9 programmable interrupt inputs 4 high sink outputs 13 alternate functions emi filtering n software or hardware watchdog (wdg) n two 16-bit timers, each featuring: 2 input captures 1) 2 output compares 1) external clock input (on timer a) pwm and pulse generator modes n synchronous serial peripheral interface (spi) n asynchronous serial communications interface (sci) n 8-bit data manipulation n 63 basic instructions and 17 main addressing modes n 8 x 8 unsigned multiply instruction n true bit manipulation n complete development support on dos/ windows tm real-time emulator n full software package on dos/windows tm (c-compiler, cross-assembler, debugger) note: 1. one only on timer a. device summary tqfp44 psdip42 csdip42w features ST72121j2 ST72121j4 program memory - bytes 8k 16k ram (stack) - bytes 384 (256) 512 (256) peripherals watchdog, timers, spi, sci and optional low voltage detector reset operating supply 3 to 6 v cpu frequency 8 mhz max (16 mhz oscillator) temperature range - 40 cto+85 c package tqfp44 - sdip42 otp/eprom devices st72t121j4/st72e121j4 1 rev. 1.4
2/89 table of contents 89 ST72121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 general description . . . . ..................................................4 1.1 introduction . . . . . . . . . . . . . . ...........................................4 1.2 pin description .......................................................5 1.3 memorymap ..........................................................7 1.4 option byte . . . . ......................................................10 2 central processing unit .................................................11 2.1 introduction . . . . . . . . . . . . . . ..........................................11 2.2 main features . . . . . . . . ...............................................11 2.3 cpu registers . . . . . . . . ...............................................11 3 clocks, reset, interrupts & power saving modes . . . .....................14 3.1 clocksystem........................................................14 3.1.1 general description .................................................14 3.1.2 external clock . . . . .................................................14 3.2 reset ................................................................15 3.2.1 introduction . . . . . . . . ...............................................15 3.2.2 external reset . . . . . ................................................15 3.2.3 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .........................15 3.2.4 low voltage detector reset ..........................................16 3.3 interrupts . . . . ......................................................17 3.4 power saving modes .................................................20 3.4.1 introduction . . . . . . . . ...............................................20 3.4.2 slowmode ........................................................20 3.4.3 waitmode ........................................................20 3.4.4 haltmode.........................................................21 3.5 miscellaneous register . . . ..........................................22 4 on-chip peripherals . . . ...................................................23 4.1 i/oports.............................................................23 4.1.1 introduction . . . . . . . . ...............................................23 4.1.2 functional description . . . . ...........................................23 4.1.3 register description .................................................27 4.2 watchdog timer (wdg) . . . . ...........................................29 4.2.1 introduction . . . . . . . . ...............................................29 4.2.2 main features . . . . .................................................29 4.2.3 functional description . . . . ...........................................30 4.2.4 hardware watchdog option . . .........................................30 4.2.5 register description .................................................30 4.3 16-bittimer ..........................................................31 4.3.1 introduction . . . . . . . . ...............................................31 4.3.2 main features . . . . .................................................31 4.3.3 functional description . . . . ...........................................31 4.3.4 register description .................................................41 4.4 serial communications interface (sci) . . . . . . . . . . . . . . .................46 4.4.1 introduction . . . . . . . . ...............................................46 4.4.2 main features . . . . .................................................46 2
3/89 table of contents 4.4.3 general description .................................................46 4.4.4 functional description . . . . ...........................................48 4.4.5 register description .................................................53 4.5 serial peripheral interface (spi) . . . . . . . . ............................57 4.5.1 introduction . . . . . . . . ...............................................57 4.5.2 main features . . . . .................................................57 4.5.3 general description . . . . . . . . . . . . .....................................57 4.5.4 functional description . . . . ...........................................59 4.5.5 register description .................................................66 5 instruction set . . . . ......................................................69 5.1 st7 addressing modes . . . . ...........................................69 5.1.1 inherent . . . . ......................................................70 5.1.2 immediate . . . . . . . . . . . . . . ..........................................70 5.1.3 direct ............................................................70 5.1.4 indexed (no offset, short, long) . . . . . . . . . . . ............................70 5.1.5 indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . .......................70 5.1.6 indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.1.7 relative mode (direct, indirect) . . . . . . . . . . . .............................71 5.2 instruction groups . . . . . . . . . . . . .....................................72 6 electrical characteristics . . . ...........................................75 6.1 absolute maximum ratings . . .........................................75 6.2 recommended operating conditions. . . ..............................76 6.3 dc electrical characteristics ......................................77 6.4 oscillator characteristics . . . . . ....................................78 6.5 peripheral characteristics . . . . . ....................................78 7 general information . . . . . ................................................84 7.1 eprom erasure ......................................................84 7.2 package mechanical data . . . .........................................85 7.3 ordering information . . . . ...........................................87 7.3.1 transfer of customer code. . .........................................87 3
4/89 ST72121 1 general description 1.1 introduction the ST72121 hcmos microcontroller unit (mcu) is a member of the st7 family. the device is based on an industry-standard 8-bit core and fea- tures an enhanced instruction set. the device is normally operated at a 16 mhz oscillator frequen- cy. under software control, the ST72121 may be placed in either wait, slow or halt modes, thus re- ducing power consumption. the enhanced in- struction set and addressing modes afford real programming potential. in addition to standard 8-bit data management, the ST72121 features true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes on the whole mem- ory. the device includes a low consumption and fast start on-chip oscillator, cpu, program memo- ry (rom/otp/eprom versions), ram, 32 i/o lines, a low voltage detector (lvd) and the fol- lowing on-chip peripherals: industry standard syn- chronous spi and asynchronous sci serial inter- faces, digital watchdog, two independent 16-bit timers, one featuring an external clock input, and both featuring pulse generator capabilities, 2 in- put captures and 2 output compares (only 1 input capture and 1 output compare on timer a). figure 1. ST72121 block diagram 8-bit core alu address and data bus oscin oscout reset port b timer b port c spi port e sci port d wat chdog pb0 -> pb4 pc0 -> pc7 pe0 -> pe1 pd0 -> pd5 osc internal clock control ram (384 - 512 bytes) port f pf0 -> pf2,4,6,7 timer a port a pa3 -> pa7 (6 bits) and lvd (6 bits) (8 bits) v ss v dd power supply program (8 - 16k bytes) memory (2 bits) (5 bits) (5 bits) 4
5/89 ST72121 1.2 pin description figure 2. 44-pin thin qfp package pinout figure 3. 42-pin shrink dip package pinout 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 (ei1) (ei1) (ei1) 20 21 22 clkout/pf0 pf1 pf2 ocmp1_a/pf4 icap1_a/pf6 pc1/ocmp1_b pc2/icap2_b extclk_a/pf7 v dd_0 v ss_0 pc0/ocmp2_b pc3/icap1_b pc4/miso pc5/mosi pb4 pd0 pd5 pd1 pd2 pd3 pd4 v dd_3 v ss_3 reset test/v pp 1) pa7 pa6 pa5 pc7/ss pc6/sck pa4 v ss_1 v dd_1 pa3 pb3 pb2 pb1 pb0 pe0/td0 v dd_2 oscin oscout v ss_2 pe1/rdi (ei3) (ei2) (ei2) (ei2) (ei2) (ei0) 1. v pp on epr om/otp only 15 16 17 18 19 20 21 clkout/pf0 pf1 pf2 ocmp1_a/pf4 icap1_a/pf6 pc1/ocmp1_b pc2/icap2_b extclk_a/pf7 reset test/v pp 1) pa7 pa6 pa5 pc7/ss pc6/sck 28 27 26 25 24 23 22 pc0/ocmp2_b pc3/icap1_b pc4/miso pc5/mosi pa4 v ss_1 v d d_1 pa3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 29 30 31 32 33 34 pb4 pd0 pd5 pd1 pd2 pd3 pb3 pb2 pb1 pb0 pe0/td0 v d d_2 oscin oscout v ss_2 42 41 40 39 38 37 36 35 pd4 v dd_3 v ss_3 pe1/rdi (ei3) (ei1) (ei1) (ei1) (ei0) (ei2) (ei2) (ei2) (ei2) 1. v pp on epr om/otp only 5
6/89 ST72121 table 1. ST72121jx pin description note 1: v pp on eprom/otp only. pin n qfp44 pin n sdip42 pin name type description remarks 1 38 pe1/rdi i/o port e1 or sci receive data in 2 39 pb0 i/o port b0 external interrupt: ei2 3 40 pb1 i/o port b1 external interrupt: ei2 4 41 pb2 i/o port b2 external interrupt: ei2 5 42 pb3 i/o port b3 external interrupt: ei2 6 1 pb4 i/o port b4 external interrupt: ei3 7 2 pd0 i/o port d0 8 3 pd1 i/o port d1 9 4 pd2 i/o port d2 10 5 pd3 i/o port d3 11 6 pd4 i/o port d4 12 7 pd5 i/o port d5 13 8 v dd_3 s main power supply 14 9 v ss_3 s ground 15 10 pf0/clkout i/o port f0 or cpu clock output external interrupt: ei1 16 11 pf1 i/o port f1 external interrupt: ei1 17 12 pf2 i/o port f2 external interrupt: ei1 18 13 pf4/ocmp1_a i/o port f4 or timer a output compare 1 19 14 pf6/icap1_a i/o port f6 or timer a input capture 1 20 15 pf7/extclk_a i/o port f7 or external clock on timer a 21 v dd_0 s main power supply 22 v ss_0 s ground 23 16 pc0/ocmp2_b i/o port c0 or timer b output compare 2 24 17 pc1/ocmp1_b i/o port c1 or timer b output compare 1 25 18 pc2/icap2_b i/o port c2 or timer b input capture 2 26 19 pc3/icap1_b i/o port c3 or timer b input capture 1 27 20 pc4/miso i/o port c4 or spi master in / slave out data 28 21 pc5/mosi i/o port c5 or spi master out / slave in data 29 22 pc6/sck i/o port c6 or spi serial clock 30 23 pc7/ss i/o port c7 or spi slave select 31 24 pa3 i/o port a3 external interrupt: ei0 32 25 v dd_1 s main power supply 33 26 v ss_1 s ground 34 27 pa4 i/o port a4 high sink 35 28 pa5 i/o port a5 high sink 36 29 pa6 i/o port a6 high sink 37 30 pa7 i/o port a7 high sink 38 31 test/v pp 1) s test mode pin. in the eprom programming mode, this pin acts as the programming voltage input v pp. this pin must be tied low in user mode 39 32 reset i/o bidirectional. active low. top priority non maskable interrupt. 40 33 v ss_2 s ground 41 34 oscout o input/output oscillator pin. these pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator. 42 35 oscin i 43 36 v dd_2 s main power supply 44 37 pe0/tdo i/o port e0 or sci transmit data out 6
7/89 ST72121 1.3 memory map figure 4. program memory map table 2. interrupt vector map vector address description remarks ffe0-ffe1h ffe2-ffe3h ffe4-ffe5h ffe6-ffe7h ffe8-ffe9h ffea-ff ebh ffec-ffedh ffee-ffefh fff0-ff f1h fff2-ff f3h fff4-ff f5h fff6-ff f7h fff8-ff f9h fffa-fffbh fffc-ff fdh fffe-ff ffh not used not used not used sci interrupt vector timer b interrupt vector timer a interrupt vector spi interrupt vector not used external interrupt vector ei3 (pb4) external interrupt vector ei2 (pb0:pb3) external interrupt vector ei1 (pf0:pf2) external interrupt vector ei0 (pa3) not used not used trap (software) interrupt vector reset vector internal interrupt internal interrupt internal interrupt internal interrupt internal interrupt external interrupt external interrupt external interrupt external interrupt cpu interrupt 0000h interrupt & reset vectors hw registers 027fh 0080h short addressing ram (zero page) 16-bit addressing ram 007fh 0200h / 0280h reserved 0080h (see table 3) ffdfh ffe0h ffffh (see table 2) 027fh c000h bfffh 00ffh 0100h 01ffh 0200h 8k bytes e000h 16k bytes program short addressing ram (zero page) 0080h 00ffh 01ffh 01ffh 384 bytes ram 512 bytes ram 256 bytes stack/ 16-bit addressing ram 256 bytes stack/ 16-bit addressing ram 0100h memory program memoryl 7
8/89 ST72121 table 3. hardware register memory map address block register label register name reset status remarks 0000h 0001h 0002h port a padr paddr paor data register data direction register option register 00h 00h 00h r/w r/w r/w 1) 0003h reserved area (1 byte) 0004h 0005h 0006h port c pcdr pcddr pcor data register data direction register option register 00h 00h 00h r/w r/w r/w 0007h reserved area (1 byte) 0008h 0009h 000ah port b pbdr pbddr pbor data register data direction register option register 00h 00h 00h r/w r/w r/w 1) 000bh reserved area (1 byte) 000ch 000dh 000eh port e pedr peddr peor data register data direction register option register 00h 00h 0ch r/w r/w r/w 1) 000fh reserved area (1 byte) 0010h 0011h 0012h port d pddr pdddr pdor data register data direction register option register 00h 00h 00h r/w r/w r/w 1) 0013h reserved area (1 byte) 0014h 0015h 0016h port f pfdr pfddr pfor data register data direction register option register 00h 00h 28h r/w r/w r/w 1) 0017h to 001fh reserved area (9 bytes) 0020h miscr miscellaneous register 00h 0021h 0022h 0023h spi spidr spicr spisr spi data i/o register spi control register spi status register xxh xxh 00h r/w r/w read only 0024h to 0029h reserved area (6 bytes) 002ah 002bh wdg wdgcr wdgsr watchdog control register watchdog status register 7fh 00h r/w r/w 3) 002ch to 0030h reserved area (5 bytes) 8
9/89 ST72121 notes: 1. the bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value. 2. external pin not available. 3. not used in versions without low voltage detector reset. 0031h 0032h 0033h 0034h-0035h 0036h-0037h 0038h-0039h 003ah-003bh 003ch-003dh 003eh-003fh timer a tacr2 tacr1 tasr taic1hr taic1lr taoc1hr taoc1lr tachr taclr taachr taaclr taic2hr taic2lr taoc2hr taoc2lr control register2 control register1 status register input capture1 high register input capture1 low register output compare1 high register output compare1 low register counter high register counter low register alternate counter high register alternate counter low register input capture2 high register input capture2 low register output compare2 high register output compare2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only 2) read only 2) r/w 2) r/w 2) 0040h reserved area (1 byte) 0041h 0042h 0043h 0044h-0045h 0046h-0047h 0048h-0049h 004ah-004bh 004ch-004dh 004eh-004fh timer b tbcr2 tbcr1 tbsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr control register2 control register1 status register input capture1 high register input capture1 low register output compare1 high register output compare1 low register counter high register counter low register alternate counter high register alternate counter low register input capture2 high register input capture2 low register output compare2 high register output compare2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h sci scisr scidr scibrr scicr1 scicr2 scierpr scietpr sci status register sci data register sci baud rate register sci control register 1 sci control register 2 sci extended receive prescaler register reserved sci extended transmit prescaler register c0h xxh 00x----xb xxh 00h 00h --- 00h read only r/w r/w r/w r/w r/w reserved r/w 0058h to 007fh reserved area (40 bytes) address block register label register name reset status remarks 9
10/89 ST72121 1.4 option byte the user has the option to select software watch- dog or hardware watchdog (see description in the watchdog chapter). when programming eprom or otp devices, this option is selected in a menu by the user of the eprom programmer before burning the eprom/otp. the option byte is lo- cated in a non-user map. no address has to be specified. the option byte is at ffh after uv eras- ure and must be properly programmed to set de- sired options. for rom devices, the option (software or hard- ware watchdog) must be specified in the option list provided to stmicroelectronics with the rom code (see ordering information). the option byte is hardware programmed as the rom content. optbyte bit 7:4 = not used bit 3 = reserved, must be cleared. bit 2 = reserved, must be set on ST72121n devic- es and must be cleared on ST72121j devices. bit 1 = not used bit 0 = wdg watchdog disable 0: the watchdog is enabled after reset (hardware watchdog). 1: the watchdog is not enabled after reset (soft- ware watchdog). 70 - - - - b3 b2 - wdg 10
11/89 ST72121 2 central processing unit 2.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 main features n 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes (with indirect addressing mode) n two 8-bit index registers n 16-bit stack pointer n 8 mhz cpu internal frequency n low power modes n maskable hardware interrupts n non-maskable software interrupt 2.3 cpu registers the 6 cpu registers shown in figure 1 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede in- struction (pre) to indicate that the following in- struction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 5. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 1 1 hi nz reset value = reset vector @ fffeh-ffff h 70 70 70 0 7 15 8 pch pcl 15 87 0 reset value = stack higher address reset value = 10 11x101 reset value = xxh reset value = xxh reset value = xxh x = undefined value 11
12/89 ST72121 central processing unit (cont'd) condition code register (cc) read/write reset value: 111x1010 the 8-bit condition code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 3 = i interrupt mask . this bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret in- structions and is tested by the jrm and jrnm in- structions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptable because the i bit is set by hardware when you en- ter it and reset by the iret instruction at the end of the interrupt routine. if the i bit is cleared by soft- ware in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the abit test and brancho, shift and rotate instructions. 70 111h inzc 12
13/89 ST72121 central processing unit (cont'd) stack pointer (sp) read/write reset value: 01ffh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 6). since the stack is 256 bytes deep, the 8th most significant bits are forced by hardware. following an mcu reset, or after a reset stack pointer in- struction (rsp), the stack pointer contains its re- set value (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 6. when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 6. stack manipulation example 15 8 00000001 70 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h stack higher address = 01ffh stack lower address = 0100h 13
14/89 ST72121 3 clocks, reset, interrupts & power saving modes 3.1 clock system 3.1.1 general description the mcu accepts either a crystal or ceramic reso- nator, or an external clock signal to drive the inter- nal oscillator. the internal clock (f cpu ) is derived from the external oscillator frequency (f osc ) . the external oscillator clock is first divided by 2, and an additional division factor of 2, 4, 8, or 16 can be applied, in slow mode, to reduce the frequency of the f cpu ; this clock signal is also routed to the on- chip peripherals. the cpu clock signal consists of a square wave with a duty cycle of 50%. the internal oscillator is designed to operate with an at-cut parallel resonant quartz crystal resona- tor in the frequency range specified for f osc .the circuit shown in figure 8 is recommended when using a crystal, and table 4 lists the recommend- ed capacitance and feedback resistance values. the crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. use of an external cmos oscillator is recom- mended when crystals outside the specified fre- quency ranges are to be used. 3.1.2 external clock an external clock may be applied to the oscin in- put with the oscout pin not connected, as shown on figure 7. table 4 recommended values for 16 mhz crystal resonator (c 0 < 7pf) r smax : parasitic series resistance of the quartz crystal (upper limit). c 0 : parasitic shunt capacitance of the quartz crys- tal (upper limit 7pf). c oscout ,c oscin : maximum total capacitance on pins oscin and oscout (the value includes the external capacitance tied to the pin plus the para- sitic capacitance of the board and of the device). r p : external shunt resistance. recommended val- ue for oscillator stability is 1m w. figure 7. external clock source connections figure 8. crystal/ceramic resonator figure 9. clock prescaler block diagram r smax 40 w 60 w 150 w c oscin 56pf 47pf 22pf c oscout 56pf 47pf 22pf r p 1-10 m w 1-10 m w 1-10 m w oscin oscout external clock nc oscin oscout c oscin c oscout r p oscin oscout c oscin c oscout r p %2 % 2,4,8, 16 f cpu to cpu and peripherals 14
15/89 ST72121 3.2 reset 3.2.1 introduction there are four sources of reset: reset pin (external source) power-on reset (internal source) watchdog (internal source) low voltage detection reset (internal source) the reset service routine vector is located at ad- dress fffeh-ffffh. 3.2.2 external reset the reset pin is both an input and an open-drain output with integrated pull-up resistor. when one of the internal reset sources is active, the reset pin is driven low to reset the whole application. 3.2.3 reset operation the duration of the reset condition, which is also reflected on the output pin, is fixed at 4096 internal cpu clock cycles. a reset signal originating from an external source must have a duration of at least 1.5 internal cpu clock cycles in order to be recog- nised. at the end of the power-on reset cycle, the mcu may be held in the reset condition by an ex- ternal reset signal. the reset pin may thus be used to ensure v dd has risen to a point where the mcu can operate correctly before the user pro- gram is run. following a power-on reset event, or after exiting halt mode, a 4096 cpu clock cycle delay period is initiated in order to allow the oscil- lator to stabilise and to ensure that recovery has taken place from the reset state. during the reset cycle, the device reset pin acts as an output that is pulsed low. in its high state, an internal pull-up resistor is connected to the reset pin. this resistor can be pulled low by external cir- cuitry to reset the device. figure 10. reset block diagram internal reset watchdog reset oscillator signal counter reset to st7 reset power-on reset v dd low voltage detector reset 15
16/89 ST72121 reset (cont'd) 3.2.4 low voltage detector reset the on-chip low voltage detector (lvd) gener- ates a static reset when the supply voltage is be- low a reference value. the lvd functions both during power-on as well as when the power supply drops (brown-out). the reference value for a volt- age drop is lower than the reference value for pow- er-on in order to avoid a parasitic reset when the mcu starts running and sinks current on the sup- ply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: v lvdup when v dd is rising v lvddown when v dd is falling provided the minimun v dd value (guaranteed for the oscillator frequency) is above v lvddown ,the mcu can only be in two modes: - under full software control or - in static safe reset in this condition, secure operation is always en- sured for the application without the need for ex- ternal reset hardware. during a low voltage detector reset, thereset pin is held low, thus permitting the mcu to reset other devices. figure 11.low voltage detector reset function figure 12. low voltage detector reset signal note: see electrical characteristics for values of v lvdup and v lvddown figure 13. temporization timing diagram after an internal reset low voltage detector reset v dd from watchdog reset reset reset v dd v lvdup v lvddown v dd addresses $fffe temporization (4096 cpu clock cycles) v lvdup 16
17/89 ST72121 3.3 interrupts the st7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the interrupt mapping table and a non- maskable software interrupt (trap). the interrupt processing flowchart is shown infigure 14. the maskable interrupts must be enabled clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsec- tion). when an interrupt has to be serviced: normal processing is suspended at the end of the current instruction execution. the pc, x, a and cc registers are saved onto the stack. the i bit of the cc register is set to prevent addi- tional interrupts. the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the interrupt mapping table for vector address- es). the interrupt service routine should finish with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit will be cleared and the main program will resume. priority management by default, a servicing interrupt can not be inter- rupted because the i bit is set by hardware enter- ing in interrupt routine. in the case several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the interrupt mapping ta- ble). non maskable software interrupts this interrupt is entered when the trap instruc- tion is executed regardless of the state of the i bit. it will be serviced according to the flowchart on figure 14. interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specific men- tioned interrupts allow the processor to leave the halt low power mode (refer to the aexit from halta column in the interrupt mapping table). external interrupts external interrupt vectors can be loaded in the pc register if the corresponding external interrupt oc- curred and if the i bit is cleared. these interrupts allow the processor to leave the halt low power mode. the external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if more than one input pin of a group connected to the same interrupt line is selected simultaneously, this will be logically ored. warning: the type of sensitivity defined in the miscellaneous or interrupt register (if available) applies to the ei source. in case of an ored source (as described on the i/o ports section). a low level on an i/o pin configured as input with in- terrupt, masks the interrupt request even in case of rising-edge sensitivity. peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: the i bit of the cc register is cleared. the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: writing a0o to the corresponding bit in the status register or an access to the status register while the flag is set followed by a read or write of an associated register. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being en- abled) will therefore be lost if the clear sequence is executed. 17
18/89 ST72121 interrupts (cont'd) figure 14. interrupt processing flowchart from reset execute instruction stack pc, x, a, cc set i bit load pc from interrupt vector restore pc, x, a, cc from stack interrupt n y bit i set n y iret fetch next instruction y n this clears i bit by default vr01172d 18
19/89 ST72121 table 5. interrupt mapping source block description register label flag exit from halt vector address priority order reset reset n/a n/a yes fffeh-ffffh trap software n/a n/a no fffch-fffdh not used fffah-fffbh not used fff8h-fff9h ei0 ext. interrupt (ports pa0:pa3) n/a n/a yes fff6h-fff7h ei1 ext. interrupt (ports pf0:pf2) n/a n/a fff4h-fff5h ei2 ext. interrupt (ports pb0:pb3) n/a n/a fff2h-fff3h ei3 ext. interrupt (ports pb4:pb7) n/a n/a fff0h-fff1h not used ffeeh-ffefh spi transfer complete spisr spif no ffech-ffedh mode fault modf timer a input capture 1 tasr icf1_a ffeah-ffebh output compare 1 ocf1_a input capture 2 icf2_a output compare 2 ocf2_a timer overflow tof_a timer b input capture 1 tbsr icf1_b ffe8h-ffe9h output compare 1 ocf1_b input capture 2 icf2_b output compare 2 ocf2_b timer overflow tof_b sci transmit buffer empty scisr tdre ffe6h-ffe7h transmit complete tc receive buffer full rdrf idle line detect idle overrun or not used ffe4h-ffe5h not used ffe2h-ffe3h not used ffe0h-ffe1h highest priority priority lowest 19
20/89 ST72121 3.4 power saving modes 3.4.1 introduction there are three power saving modes. slow mode is selected by setting the relevant bits in the mis- cellaneous register. wait and halt modes may be entered using the wfi and halt instructions. 3.4.2 slow mode in slow mode, the oscillator frequency can be di- vided by a value defined in the miscellaneous register. the cpu and peripherals are clocked at this lower frequency. slow mode is used to reduce power consumption, and enables the user to adapt clock frequency to available supply voltage. 3.4.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. all peripher- als remain active. during wait mode, the i bit (cc register) is cleared, so as to enable all interrupts. all other registers and memory remain unchanged. the mcu will remain in wait mode until an inter- rupt or reset occurs, whereupon the program counter branches to the starting address of the in- terrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 15 below. figure 15. wait flow chart wfi instruction reset interrupt y n n y cpu clock oscillator periph. clock i-bit on on cleared off note: before servicing an interrupt, the cc register is pushed on the stack. the i-bit is set during the inter- rupt routine and cleared when the cc register is popped. 4096 cpu clock fetch reset vector or service interrupt cycles delay cpu clock oscillator periph. clock i-bit on on set on cpu clock oscillator periph. clock i-bit on on set on 20
21/89 ST72121 power saving modes (cont'd) 3.4.4 halt mode the halt mode is the mcu lowest power con- sumption mode. the halt mode is entered by exe- cuting the halt instruction. the internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. the halt mode cannot be used when the watchdog is enabled, if the halt instruction is executed while the watchdog system is enabled, a watchdog reset is generated thus resetting the en- tire mcu. when entering halt mode, the i bit in the cc reg- ister is cleared so as to enable external interrupts. if an interrupt occurs, the cpu becomes active. the mcu can exit the halt mode upon reception of an interrupt or a reset. refer to the interrupt map- ping table. the oscillator is then turned on and a stabilization time is provided before releasing cpu operation. the stabilization time is 4096 cpu clock cycles. after the start up delay, the cpu continues oper- ation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. figure 16. halt flow chart n n external interrupt 1) reset halt instruction 4096 cpu clock fetch reset vector or service interrupt cycles delay cpu clock oscillator periph. clock 2) i-bit on off set on cpu clock oscillator periph. clock i-bit off off cleared off y y wdg enabled? n y reset watchdog 1) or some specific interrupts note: before servicing an interrupt, the cc register is pushed on the stack. the i-bit is set during the inter- rupt routine and cleared when the cc register is popped. cpu clock oscillator periph. clock i-bit on on set on 2) if reset periph. clock = on ; if interrupt periph. clock = off 21
22/89 ST72121 3.5 miscellaneous register the miscellaneous register allows to select the slow operating mode, the polarity of external in- terrupt requests and to output the internal clock. register address: 0020h e read/ write reset value: 0000 0000 (00h) bit 7:6 = pei[3:2] external interrupt ei3 and ei2 polarity options . these bits are set and cleared by software. they determine which event on ei2 and ei3 causes the external interrupt according totable 6. table 6. ei2 and ei3 external interrupt polarity options bit 5 = mco main clock out this bit is set and cleared by software. when set it allows to output the internal clock on pf0 i/o. 0 - pf0 is a normal i/o port. 1-f cpu outputs on pf0 pin. bit 4:3 = pei1-pei0 external interrupt ei1 and ei0 polarity options . these bits are set and cleared by software. they determine which event on ei0 and ei1 causes the external interrupt according totable 7. table 7. ei0 and ei1 external interrupt polarity options bit 2:1 = psm[1:0] prescaler for slow mode these bits are set and cleared by software. they determine the cpu clock when the sms bit is set according to the following table. table 8. f cpu value in slow mode bit 0 = sms slow mode select this bit is set and cleared by software. 0: normal mode - f cpu =f osc /2 (reset state) 1: slow mode - the f cpu value is determined by the psm1 and psm0 bits. 70 pei3 pei2 mco pei1 pei0 psm1 psm0 sms mode pei3 pei2 falling edge and low level (reset state) 00 falling edge only 1 0 rising edge only 0 1 rising and falling edge 1 1 mode pei1 pei0 falling edge and low level (reset state) 00 falling edge only 1 0 rising edge only 0 1 rising and falling edge 1 1 f cpu value psm1 psm0 f osc /4 0 0 f osc /16 0 1 f osc /8 1 0 f osc /32 1 1 22
23/89 ST72121 4 on-chip peripherals 4.1 i/o ports 4.1.1 introduction the i/o ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: analog signal input (adc) alternate signal input/output for the on-chip pe- ripherals. external interrupt generation an i/o port is composed of up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital out- put. 4.1.2 functional description each port is associated to 2 main registers: data register (dr) data direction register (ddr) and some of them to an optional register: option register (or) each i/o pin may be programmed using the corre- sponding register bits in ddr and or registers: bit x corresponding to pin x of the port. the same cor- respondence is used for the dr register. the following description takes into account the or register, for specific ports which do not provide this register refer to the i/o port implementation section 4.1.2.5. the generic i/o block diagram is shown on figure 18. 4.1.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. notes : 1. all the inputs are triggered by a schmitt trigger. 2. when switching from input mode to output mode, the dr register should be written first to output the correct value as soon as the port is con- figured as an output. interrupt function when an i/o is configured in input with interrupt, an event on this i/o can generate an external in- terrupt request to the cpu. the interrupt polarity is given independently according to the description mentioned in the miscellaneous register or in the interrupt register (where available). each pin can independently generate an interrupt request. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see interrupts sec- tion). if more than one input pin is selected simul- taneously as interrupt source, this is logically ored. for this reason if one of the interrupt pins is tied low, it masks the other ones. 4.1.2.2 output mode the pin is configured in output mode by setting the corresponding ddr register bit. in this mode, writing a0o or a1o to the dr register applies this digital value to the i/o pin through the latch. then reading the dr register returns the previously stored value. note : in this mode, the interrupt function is disa- bled. 4.1.2.3 digital alternate function when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over standard i/o programming. when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin has to be configured in input mode. in this case, the pin's state is also digitally readable by addressing the dr register. notes: 1. input pull-up configuration can cause an unex- pected value at the input of the alternate peripher- al input. 2. when the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (ddr = 0). warning : the alternate function must not be acti- vated as long as the pin is configured as input with interrupt, in order to avoid generating spurious in- terrupts. 23
24/89 ST72121 i/o ports (cont'd) 4.1.2.4 analog alternate function when the pin is used as an adc input the i/o must be configured as input, floating. the analog multi- plexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maximum ratings. 4.1.2.5 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific feature of the i/o port such as adc in- put (see figure 18) or true open drain. switching these i/o ports from one state to another should be done in a sequence that prevents unwanted side effects. recommended safe transitions are il- lustrated in figure 17. other transitions are poten- tially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 17. recommended i/o state transition diagram with interrupt input output no interrupt input push-pull open-drain output 24
25/89 ST72121 i/o ports (cont'd) figure 18 . i/o block diagram table 9. port mode configuration legend : 0 - present, not activated 1 - present and activated notes : no or register on some ports (see register map). adc switch on ports with analog alternate functions. dr ddr latch latch data bus dr sel ddr sel v dd pad analog switch analog enable (adc) m u x alternate alternate alternate enable common analog rail alternate m u x alternate input pull-up (s ee t able below ) output p-buffer (s ee t able b elow ) n-buffer 1 0 1 0 or latch or sel from other bits external pull-up condition enable enable gnd (s ee t able below ) (s ee n ote below ) cmos schmitt trigger source (eix) interrupt polarity sel configu ration mode pull-up p-buffer floating 0 0 pull-up 1 0 push-pull 0 1 true open drain not present not present open drain (logic level) 0 0 25
26/89 ST72121 i/o ports (cont'd) table 10. port configuration * reset state (the bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value). warning: all bits of the ddr register which correspond to unconnected i/os must be left at their reset value. they must not be modified by the user otherwise a spurious interrupt may be generated. port pin name input (ddr = 0) output (ddr = 1) or = 0 or = 1 or = 0 or =1 port a pa3 floating* pull-up with interrupt open-drain push-pull pa4:pa7 floating* true open drain, high sink capability port b pb0:pb4 floating* pull-up with interrupt open-drain push-pull port c pc0:pc7 floating* pull-up open-drain push-pull port d pd0:pd5 floating* pull-up open-drain push-pull port e pe0:pe1 floating* pull-up open-drain push-pull port f pf0:pf2 floating* pull-up with interrupt open-drain push-pull pf4, pf6, pf7 floating* pull-up open-drain push-pull 26
27/89 ST72121 i/o ports (cont'd) 4.1.3 register description 4.1.3.1 data registers port a data register (padr) port b data register (pbdr) port c data register (pcdr) port d data register (pddr) port e data register (pedr) port f data register (pfdr) read/write reset value: 0000 0000 (00h) bit 7:0 = d7-d0 data register 8 bits. the dr register has a specific behaviour accord- ing to the selected input/output configuration. writ- ing the dr register is always taken in account even if the pin is configured as an input. reading the dr register returns either the dr register latch content (pin configured as output) or the digital val- ue applied to the i/o pin (pin configured as input). 4.1.3.2 data direction registers port a data direction register (paddr) port b data direction register (pbddr) port c data direction register (pcddr) port d data direction register (pdddr) port e data direction register (peddr) port f data direction register (pfddr) read/write reset value: 0000 0000 (00h) (input mode) bit 7:0 = dd7-dd0 data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bits is set and cleared by software. 0: input mode 1: output mode 4.1.3.3 option registers port a option register (paor) port b option register (pbor) port c option register (pbor) port d option register (pbor) port e option register (pbor) port f option register (pfor) read/write reset value: see register memory maptable 3 bit 7:0 = o7-o0 option register 8 bits. the or register allow to distinguish in input mode if the interrupt capability or the floating configura- tion is selected. in output mode it select push-pull or open-drain capability. each bit is set and cleared by software. input mode: 0: floating input 1: input pull-up with interrupt output mode: 0: open-drain configuration 1: push-pull configuration 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 70 o7 o6 o5 o4 o3 o2 o1 o0 27
28/89 ST72121 i/o ports (cont'd) table 11. i/o port register map address (hex.) register label 76543210 0000h padr d7 d6 d5 d4 d3 d2 d1 d0 0001h paddr dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 0002h paor o7 o6 o5 o4 o3 o2 o1 o0 0004h pcdr d7 d6 d5 d4 d3 d2 d1 d0 0005h pcddr dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 0006h pcor o7 o6 o5 o4 o3 o2 o1 o0 0008h pbdr d7 d6 d5 d4 d3 d2 d1 d0 0009h pbddr dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 000ah pbor o7 o6 o5 o4 o3 o2 o1 o0 000ch pedr d7 d6 d5 d4 d3 d2 d1 d0 000dh peddr dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 000eh peor o7 o6 o5 o4 o3 o2 o1 o0 0010h pddr d7 d6 d5 d4 d3 d2 d1 d0 0011h pdddr dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 0012h pdor o7 o6 o5 o4 o3 o2 o1 o0 0014h pfdr d7 d6 d5 d4 d3 d2 d1 d0 0015h pfddr dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 0016h pfor o7 o6 o5 o4 o3 o2 o1 o0 28
29/89 ST72121 4.2 watchdog timer (wdg) 4.2.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counter's contents before the t6 bit be- comes cleared. 4.2.2 main features n programmable timer (64 increments of 12288 cpu cycles) n programmable reset n reset (if watchdog activated) after a halt instruction or when the t6 bit reaches zero n hardware watchdog selectable by option byte. n watchdog reset indicated by status flag (in versions with safe reset option only) figure 19. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) 12288 t1 t2 t3 t4 t5 29
30/89 ST72121 watchdog timer (cont'd) 4.2.3 functional description the counter value stored in the cr register (bits t6:t0), is decremented every 12,288 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t6:t0) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. the value to be stored in the cr register must be between ffh and c0h (see table 12): the wdga bit is set (watchdog enabled) the t6 bit is set to prevent generating an imme- diate reset the t5:t0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. table 12. watchdog timing (f cpu = 8 mhz) notes: following a reset, the watchdog is disa- bled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. 4.2.4 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. refer to the device-specific option byte descrip- tion. 4.2.5 register description control register (cr) read/ write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watch- dog otion is enabled by option byte. bit 6-0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 become cleared). status register (sr) read/ write reset value*: 0000 0000 (00h) bit 0 = wdogf watchdog flag . this bit is set by a watchdog reset and cleared by software or a power on/off reset. this bit is useful for distinguishing power/on off or external reset and watchdog reset. 0: no watchdog reset occurred 1: watchdog reset occurred * only by software and power on/off reset note: this register is not used in versions without lvd reset. table 13. wdg register map cr register initial value wdg timeout period (ms) max ffh 98.304 min c0h 1.536 70 wdga t6 t5 t4 t3 t2 t1 t0 70 - ------wdogf address (hex.) register name 76543210 2a cr wdga t6.. t0 2b sr -- -----wdogf 30
31/89 ST72121 4.3 16-bit timer 4.3.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input sig- nals ( input capture ) or generation of up to two out- put waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the cpu clock prescaler. 4.3.2 main features n programmable prescaler: f cpu divided by 2, 4 or 8. n overflow status flag and maskable interrupt n external clock input (must be at least 4 times slower than the cpuclock speed) with the choice of active edge n output compare functions with 2 dedicated 16-bit registers 2 dedicated programmable signals 2 dedicated status flags 1 dedicated maskable interrupt n input capture functions with 2 dedicated 16-bit registers 2 dedicated active edge selection signals 2 dedicated status flags 1 dedicated maskable interrupt n pulse width modulation mode (pwm) n one pulse mode n 5 alternate functions on i/o ports* the block diagram is shown infigure 1. *note: some external pins are not available on all devices. refer to the device pin out description. when reading an input signal which is not availa- ble on an external pin, the value will always be `1'. 4.3.3 functional description 4.3.3.1 counter the principal block of the programmable timer is a 16-bit free running increasing counter and its as- sociated 16-bit registers: counter registers counter high register (chr) is the most sig- nificant byte (msb). counter low register (clr) is the least sig- nificant byte (lsb). alternate counter registers alternate counter high register (achr) is the most significant byte (msb). alternate counter low register (aclr) is the least significant byte (lsb). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (overflow flag), (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. the timer clock depends on the clock control bits of the cr2 register, as illustrated intable 1. the value in the counter register repeats every 131.072, 262.144 or 524.288 internal processor clock cycles depending on the cc1 and cc0 bits. 31
32/89 ST72121 16-bit timer (cont'd) figure 20. timer block diagram mcu-peripheral interface counter alternate register output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 0 0 0 ocf2 ocf1tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 cr1 cr2 sr 6 16 888 8 88 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture registe r 2 cc1 cc0 16 bit free running counter 32
33/89 ST72121 16-bit timer (cont'd) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the msb first, then the lsb value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the msb several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the lsb of the count value at the time of the read. an overflow occurs when the counter rolls over from ffffh to 0000h then: the tof bit of the sr register is set. a timer interrupt is generated if: toie bit of the cr1 register is set and i bit of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. notes: the tof bit is not cleared by accesses to aclr register. this feature allows simultaneous use of the overflow function and reads of the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 4.3.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in cr2 register. the status of the exedg bit determines the type of level transition on the external clock pin ext- clk that will trigger the free running counter. the counter is synchronised with the falling edge of the internal cpu clock. at least four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock frequen- cy must be less than a quarter of the cpu clock frequency. lsb is buffered read msb at t0 read lsb returns the buffered lsb value at t0 at t0 + d t other instructions beginning of the sequence sequence completed 33
34/89 ST72121 16-bit timer (cont'd) figure 21. counter timing diagram, internal clock divided by 2 figure 22. counter timing diagram, internal clock divided by 4 figure 23. counter timing diagram, internal clock divided by 8 cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register overflow flag tof fffc fffd 0000 0001 cpu clock internal reset timer clock counter register overflow flag tof cpu clock internal reset timer clock counter register overflow flag tof fffc fffd 0000 34
35/89 ST72121 16-bit timer (cont'd) 4.3.3.3 input capture in this section, the index, i , may be 1 or 2. the two input capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition detected by the icap i pin (see figure 5). ic i rregister is a read-only register. the active transition is software programmable through the iedg i bit of the control register (cr i ). timing resolution is one count of the free running counter: ( f cpu /(cc1.cc0) ). procedure to use the input capture function select the follow- ing in the cr2 register: select the timer clock (cc1-cc0) (seetable 1). select the edge of the active transition on the icap2 pin with the iedg2 bit. and select the following in the cr1 register: set the icie bit to generate an interrupt after an input capture. select the edge of the active transition on the icap1 pin with the iedg1 bit. when an input capture occurs: icf i bit is set. theic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 6). a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. other- wise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. note: after reading the ic i hr register, transfer of input capture data is inhibited until the ic i lr regis- ter is also read. the ic i r register always contains the free running counter value which corresponds to the most re- cent input capture. during halt mode, if at least one valid input cap- ture edge occurs on the icap i pin, the input cap- ture detection circuitry is armed. this does not set any timer flags, and does not awake-upo the mcu. if the mcu is awoken by an interrupt, the input capture flag will become active, and data corre- sponding to the first valid edge during halt mode will be present. ms byte ls byte icir ic i hr ic i lr 35
36/89 ST72121 16-bit timer (cont'd) figure 24. input capture block diagram figure 25. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r ic2r edge detect circuit1 ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: a ctive edge is rising edge. 36
37/89 ST72121 16-bit timer (cont'd) 4.3.3.4 output compare in this section, the index, i , may be 1 or 2. this function can be used to control an output waveform or indicating when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: assigns pins with a programmable value if the ocie bit is set sets a flag in the status register generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the free run- ning counter each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/(cc1.cc0) ). procedure to use the output compare function, select the fol- lowing in the cr2 register: set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i function. select the timer clock (cc1-cc0) (seetable 1). and select the following in the cr1 register: select the olvl i bit to applied to the ocmp i pins after the match occurs. set the ocie bit to generate an interrupt if it is needed. when match is found: ocf i bit is set. the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset and stays low until valid compares change it to a high level). a timer interrupt is generated if the ocie bit is set in the cr2 register and the i bit is cleared in the cc register (cc). clearing the output compare interrupt request is done by: 3. reading the sr register while the ocf i bit is set. 4. an access (read or write) to the oc i lr register. note: after a processor write cycle to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. if the oc i e bit is not set, the ocmp i pin is a gen- eral i/o port and the olvl i bit will not appear when match is found but an interrupt could be gen- erated if the ocie bit is set. the value in the 16-bit oc i r register and the olv i bit should be changed after each successful com- parison in order to control an output waveform or establish a new elapsed timeout. when the clock is divided by 2, ocf i and ocmp i are set while the counter value equals the oc i r register value (see figure 8). this behaviour is the same in opm or pwm mode. when the clock is divided by 4, 8 or in external clock mode , ocf i and ocmp i are set while the counter value equals the oc i r register value plus 1 (see figure 9). the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: d t = desired output compare period (in seconds) f cpu = internal clock frequency t presc = timer clock prescaler (cc1-cc0 bits, see table 1) the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: write to the oc i hr register (further compares are inhibited). read the sr register (first step of the clearance of the ocf i bit, which may be already set). write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr d oc i r= d t * f cpu t presc 37
38/89 ST72121 16-bit timer (cont'd) figure 26. output compare block diagram figure 27. output compare timing diagram, internal clock divided by 2 figure 28. output compare timing diagram, internal clock divided by 4 output compare 16-bit circuit oc1r 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r internal cpu clock timer clock counter output compare register output compare flag (ocfi) ocmpi pin (olvli=1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter output compare register compare register latch ocfi and ocmpi pin (olvli=1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf 38
39/89 ST72121 16-bit timer (cont'd) 4.3.3.5 forced compare mode in this section i may represent 1 or 2. the following bits of the cr1 register are used: when the folv i bit is set, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is not set, and thus no interrupt re- quest is generated. 4.3.3.6 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure to use one pulse mode: 1. load the oc1r register with the value corre- sponding to the length of the pulse (see the for- mula in section 0.1.3.7). 2. select the following in the the cr1 register: using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. select the edge of the active transition on the icap1 pin with the iedg1 bit . 3. select the following in the cr2 register: set the oc1e bit, the ocmp1 pin is then ded- icated to the output compare 1 function. set the opm bit. select the timer clock cc1-cc0 (seetable 1). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffch and olvl2 bit is loaded on the ocmp1 pin. when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 10). note: the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. the icf1 bit is set when an active edge occurs and can generate an interrupt if the icie bit is set. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. figure 29. one pulse mode timing folv2 folv1 olvl2 olvl1 event occurs counter is initialized to fffch ocmp1 = olvl2 counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle counter .... fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 39
40/89 ST72121 16-bit timer (cont'd) 4.3.3.7 pulse width modulation mode pulse width modulation mode enables the gener- ation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. the pulse width modulation mode uses the com- plete output compare 1 function plus the oc2r register. procedure to use pulse width modulation mode: 1. load the oc2r register with the value corre- sponding to the period of the signal. 2. load the oc1r register with the value corre- sponding to the length of the pulse if (olvl1=0 and olvl2=1). 3. select the following in the cr1 register: using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc1r register. using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc2r register. 4. select the following in the cr2 register: set oc1e bit: the ocmp1 pin is then dedicat- ed to the output compare 1 function. set the pwm bit. select the timer clock (cc1-cc0) (seetable 1). if olvl1=1 and olvl2=0 the length of the pulse is the difference between the oc2r and oc1r registers. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = desired output compare period (seconds) f cpu = internal clock frequency (see miscella- neous register) t presc = timer clock prescaler (cc1-cc0 bits , see table 1) the output compare 2 event causes the counter to be initialized to fffch (seefigure 11). note: after a write instruction to the oc i hr regis- ter, the output compare function is inhibited until the oc i lr register is also written. the icf1 bit is set by hardware when the counter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. therefore the input capture 1 function is inhibited but the input capture 2 is available. the ocf1 and ocf2 bits cannot be set by hard- ware in pwm mode therefore the output compare interrupt is inhibited. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. figure 30. pulse width modulation mode timing oc i r value = t * f cpu t presc -5 counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set counter 34e2 fffc fffd fffe 2ed0 2ed1 2ed2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r=2ed0h, oc2r=34e2, olvl1=0, olvl2= 1 40
41/89 ST72121 16-bit timer (cont'd) 4.3.4 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 41
42/89 ST72121 16-bit timer (cont'd) control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 enable. 0: output compare 1 function is enabled, but the ocmp1 pin is a general i/o. 1: output compare 1 function is enabled, the ocmp1 pin is dedicated to the output compare 1 capability of the timer. bit 6 = oc2e output compare 2 enable. 0: output compare 2 function is enabled, but the ocmp2 pin is a general i/o. 1: output compare 2 function is enabled, the ocmp2 pin is dedicated to the output compare 2 capability of the timer. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bit 3, 2 = cc1-cc0 clock control. the value of the timer clock depends on these bits: table 14. clock control bits bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin extclk will trigger the free running counter. 0: a falling edge triggers the free running counter. 1: a rising edge triggers the free running counter. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg timer clock cc1 cc0 f cpu /4 0 0 f cpu /2 0 1 f cpu /8 1 0 external clock (where available) 11 42
43/89 ST72121 16-bit timer (cont'd) status register (sr) read only reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) regis- ter. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) reg- ister. bit 5 = tof timer overflow. 0: no timer overflow (reset value). 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr reg- ister, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred.to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) reg- ister. bit 2-0 = reserved, forced by hardware to 0. input capture 1 high register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 icf1 ocf1 tof icf2 ocf2 0 0 0 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 43
44/89 ST72121 16-bit timer (cont'd) output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the sr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to sr register does not clear the tof bit in sr register. input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 44
45/89 ST72121 16-bit timer (cont'd) table 15. 16-bit timer register map and reset values address (hex.) register name 76543210 timera: 32 timerb: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timera: 31 timerb: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timera: 33 timerb: 43 sr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 - 0 - 0 - 0 timera: 34 timerb: 44 ic1hr reset value msb - ------ lsb - timera: 35 timerb: 45 ic1lr reset value msb - ------ lsb - timera: 36 timerb: 46 oc1hr reset value msb 1 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 timera: 37 timerb: 47 oc1lr reset value msb 0 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 timera: 3e timerb: 4e oc2hr reset value msb 1 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 timera: 3f timerb: 4f oc2lr reset value msb 0 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 timera: 38 timerb: 48 chr reset value msb 1111111 lsb 1 timera: 39 timerb: 49 clr reset value msb 1111110 lsb 0 timera: 3a timerb: 4a achr reset value msb 1111111 lsb 1 timera: 3b timerb: 4b aclr reset value msb 1111110 lsb 0 timera: 3c timerb: 4c ic2hr reset value msb - ------ lsb - timera: 3d timerb: 4d ic2lr reset value msb - ------ lsb - 45
46/89 ST72121 4.4 serial communications interface (sci) 4.4.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci of- fers a very wide range of baud rates using two baud rate generator systems. 4.4.2 main features n full duplex, asynchronous communications n nrz standard format (mark/space) n dual baud rate generator systems n independently programmable transmit and receive baud rates up to 250k baud. n programmable data word length (8 or 9 bits) n receive buffer full, transmit buffer empty and end of transmission flags n two receiver wake-up modes: address bit (msb) idle line n muting function for multiprocessor configurations n separate enable bits for transmitter and receiver n three error detection flags: overrun error noise error frame error n five interrupt sources with flags: transmit data register empty transmission complete receive data register full idle line received overrun error detected 4.4.3 general description the interface is externally connected to another device by two pins (see figure 2.): tdo: transmit data output. when the transmit- ter is disabled, the output pin returns to its i/o port configuration. when the transmitter is ena- bled and nothing is to be transmitted, the tdo pin is at high level. rdi: receive data input is the serial data input. oversampling techniques are used for data re- covery by discriminating between valid incoming data and noise. through this pins, serial data is transmitted and re- ceived as frames comprising: an idle line prior to transmission or reception a start bit a data word (8 or 9 bits) least significant bit first a stop bit indicating that the frame is complete. this interface uses twotypes of baud rate generator: a conventional type for commonly-used baud rates, an extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies. 46
47/89 ST72121 serial communications interface (cont'd) figure 31. sci block diagram wake up unit receiver control sr transmit control tdre tc rdrf idle or nf fe - cr2 sbk rwu re te ilie rie tcie tie sci control interrupt cr1 r8 t8 - m wake - -- received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) dr transmit ter clock receiver clock receiver rate transm itter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /2 /pr /16 conventio nal baud rate generator 47
48/89 ST72121 serial communications interface (cont'd) 4.4.4 functional description the block diagram of the serial control interface, is shown in figure 1.. it contains 6 dedicated reg- isters: two control registers (cr1 & cr2) a status register (sr) a baud rate register (brr) an extended prescaler receiver register (erpr) an extended prescaler transmitter register (etpr) refer to the register descriptions insection 0.1.5 for the definitions of each bit. 4.4.4.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the cr1 register (see figure 1.). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of a1os followed by the start bit of the next frame which contains data. a break character is interpreted on receiving a0os for some multiple of the frame period. at the end of the last break frame the transmitter inserts an ex- tra a1o bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 32. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra '1' data frame break frame start bit extra '1' data frame next data frame next data frame 48
49/89 ST72121 serial communications interface (cont'd) 4.4.4.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the cr1 reg- ister. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the dr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 1.). procedure select the m bit to define the word length. select the desired baud rate using the brr and the etpr registers. set the te bit to assign the tdo pin to the alter- nate function and to send a idle frame as first transmission. access the sr register and write the data to send in the dr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the sr register 2. a write to the dr register the tdre bit is set by hardware and it indicates: the tdr register is empty. the data transfer is beginning. the next data can be written in the dr register without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the ccr register. when a transmission is taking place, a write in- struction to the dr register stores the data in the tdr register and which is copied in the shift regis- ter at the end of the current transmission. when no transmission is taking place, a write in- struction to the dr register places the data directly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit or after the break frame) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the sr register 2. a write to the dr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit loads the shift register with a break character. the break frame length depends on the m bit (see figure 2.). as long as the sbk bit is set, the sci send break frames to the tdo pin. after clearing this bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a trans- mission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set i.e. before writing the next byte in the dr. 49
50/89 ST72121 serial communications interface (cont'd) 4.4.4.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the cr1 reg- ister. character reception during a sci reception, data shifts in least signifi- cant bit first through the rdi pin. in this mode, dr register consists in a buffer (rdr) between the in- ternal bus and the received shift register (see fig- ure 1.). procedure select the m bit to define the word length. select the desired baud rate using the brr and the erpr registers. set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. clearing the rdrf bit is performed by the following software sequence done by: 1. an access to the sr register 2. a read to the dr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the spi han- dles it as a framing error. idle character when a idle frame is detected, there is the same procedure as a data received character plus an in- terrupt if the ilie bit is set and the i bit is cleared in the ccr register. overrun error an overrun error occurs when a character is re- ceived when rdrf has not been reset. data can not be transferred from the shift register to the tdr register as long as the rdrf bit is not cleared. when a overrun error occurs: the or bit is set. the rdr content will not be lost. the shift register will be overwritten. an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the or bit is reset by an access to the sr register followed by a dr register read operation. noise error oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. when noise is detected in a frame: the nf is set at the rising edge of the rdrf bit. data is transferred from the shift register to the dr register. no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf bit is reset by a sr register read operation followed by a dr register read operation. framing error a framing error is detected when: the stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. a break is received. when the framing error is detected: the fe bit is set by hardware data is transferred from the shift register to the dr register. no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a sr register read operation followed by a dr register read operation. 50
51/89 ST72121 serial communications interface (cont'd) figure 33. sci baud rate and extended prescaler block diagram transmit ter receiver etpr erpr exten ded prescaler receiver rate control exten ded prescaler transmitter rate control extended prescaler clock clock receiver rate transmitter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /2 /pr /16 conventional baud rate generator exten ded receiver prescaler register exte nded trans mitter prescaler register 51
52/89 ST72121 serial communications interface (cont'd) 4.4.4.4 conventional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp0 & scp1 bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct0, sct1 & sct2 bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr0,scr1 & scr2 bits) all this bits are in the brr register. example: if f cpu is 8 mhz (normal mode) and if pr=13 and tr=rr=1, the transmit and receive baud rates are 19200 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is en- abled. 4.4.4.5 extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescal- er, whereas the conventional baud rate genera- tor retains industry standard software compatibili- ty. the extended baud rate generator block diagram is described in the figure 3.. the output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the erpr or the etpr register. note: the extended prescaler is activated by set- ting the etpr or erpr register to a value other than zero. the baud rates are calculated as fol- lows: with: etpr = 1,..,255 (see etpr register) erpr = 1,.. 255 (see erpr register) 4.4.4.6 receiver muting and wake-up feature in multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interrupt are inhibited. a muted receiver may be awakened by one of the following two ways: by idle line detection if the wake bit is reset, by address mark detection if the wake bit is set. receiver wakes-up by idle line detection when the receive line has recognised an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. receiver wakes-up by address mark detection when it received a a1o as the most significant bit of a word, thus indicating that the message is an ad- dress. the reception of this particular word wakes up the receiver, sets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. tx = (32 * pr) * tr f cpu rx = (32 * pr) * rr f cpu tx = 16 * etpr f cpu rx = 16 * erpr f cpu 52
53/89 ST72121 serial communications interface (cont'd) 4.4.5 register description status register (sr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie =1 in the cr2 register. it is cleared by a software se- quence (an access to the sr register followed by a write to the dr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note : data will not be transferred to the shift regis- ter as long as the tdre bit is not reset. bit 6 = tc transmission complete. this bit is set by hardware when transmission of a frame containing data, a preamble or a break is complete. an interrupt is generated if tcie=1 in the cr2 register. it is cleared by a software se- quence (an access to the sr register followed by a write to the dr register). 0: transmission is not complete 1: transmission is complete bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred into the dr register. an interrupt is generated if rie=1 in the cr2 register. it is cleared by hardware when re=0 or by a software sequence (an access to the sr register followed by a read to the dr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detect. this bit is set by hardware when a idle line is de- tected. an interrupt is generated if the ilie=1 in the cr2 register. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line oc- curs). this bit is not set by an idle line when the re- ceiver wakes up from wake-up mode. bit 3 = or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf=1. an interrupt is generated if rie=1 in the cr2 reg- ister. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr register). 0: no overrun error 1: overrun error is detected note: when this bit is set rdr register content will not be lost but the shift register will be overwritten. bit 2 = nf noise flag. this bit is set by hardware when noise is detected on a received frame. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr regis- ter). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it will be transferred and only the or bit will be set. bit 0 = unused. 70 tdre tc rdrf idle or nf fe - 53
54/89 ST72121 serial communications interface (cont'd) control register 1 (cr1) read/write reset value: undefined bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m=1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmit- ted word when m=1. bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre=1 in the sr register. bit 6 = tcie transmission complete interrupt ena- ble this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the sr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the sr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the sr register. bit 3 = te transmitter enable. this bit enables the transmitter and assigns the tdo pin to the alternate function. it is set and cleared by software. 0: transmitter is disabled, the tdo pin is back to the i/o port configuration. 1: transmitter is enabled note: during transmission, a a0o pulse on the te bit (a0o followed by a1o) sends a preamble after the current word. bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled, it resets the rdrf, idle, or, nf and fe bits of the sr register. 1: receiver is enabled and begins searching for a start bit. bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to a1o and then to a0o, the transmitter will send a break word at the end of the current word. 70 r8 t8 - m wake - - - 70 tie tcie rie ilie te re rwu sbk 54
55/89 ST72121 serial communications interface (cont'd) data register (dr) read/write reset value: undefined contains the received or transmitted data char- acter, depending on whether it is read from or writ- ten to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift reg- ister (see figure 1.). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 1.). baud rate register (brr) read/write reset value: 00xx xxxx (xxh) bit 7:6= scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bit 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in convention- al baud rate generator mode. note: this tr factor is used only when the etpr fine tuning factor is equal to 00h; otherwise, tr is replaced by the etpr dividing factor. bit 2:0 = scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. note: this rr factor is used only when the erpr fine tuning factor is equal to 00h; otherwise, rr is replaced by the erpr dividing factor. 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 70 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 pr prescaling factor scp1 scp0 100 301 410 13 1 1 tr dividing factor sct2 sct1 sct0 1000 2001 4010 8011 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 rr dividing factor scr2 scr1 scr0 1000 2001 4010 8011 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 55
56/89 ST72121 serial communications interface (cont'd) extended receive prescaler division register (erpr) read/write reset value: 0000 0000 (00h) allows setting of the extended prescaler rate divi- sion factor for the receive circuit. bit 7:1 = erpr[7:0] 8-bit extended receive pres- caler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 3.) is divided by the binary factor set in the erpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. extended transmit prescaler division register (etpr) read/write reset value:0000 0000 (00h) allows setting of the external prescaler rate divi- sion factor for the transmit circuit. bit 7:1 = etpr[7:0] 8-bit extended transmit pres- caler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 3.) is divided by the binary factor set in the etpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. table 16. sci register map and reset values 76543210 erpr 7 erpr 6 erpr 5 erpr 4 erpr 3 erpr 2 erpr 1 erpr 0 76543210 etpr 7 etpr 6 etpr 5 etpr 4 etpr 3 etpr 2 etpr 1 etpr 0 address (hex.) register name 76543210 50 sr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 0 - 0 51 dr reset value dr7 - dr6 - dr5 - dr4 - dr3 - dr2 - dr1 - dr0 - 52 brr reset value scp1 0 scp0 0 sct2 x sct1 x sct0 x scr2 x scr1 x scr0 x 53 cr1 reset value r8 - t8 -- m - wake ---- 54 cr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 55 erpr reset value erpr7 0 erpr6 0 erpr5 0 erpr4 0 erpr3 0 erpr2 0 erpr1 0 erpr0 0 57 etpr reset value etpr7 0 etpr6 0 etpr5 0 etpr4 0 etpr3 0 etpr2 0 etpr1 0 etpr0 0 56
57/89 ST72121 4.5 serial peripheral interface (spi) 4.5.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. the spi is normally used for communication be- tween the microcontroller and external peripherals or another microcontroller. refer to the pin description chapter for the device- specific pin-out. 4.5.2 main features n full duplex, three-wire synchronous transfers n master or slave operation n four master mode frequencies n maximum slave mode frequency = fcpu/2. n four programmable master bit rates n programmable clock polarity and phase n end of transfer interrupt flag n write collision flag protection n master mode fault protection capability. 4.5.3 general description the spi is connected to external devices through 4 alternate pins: miso: master in slave out pin mosi: master out slave in pin sck: serial clock pin ss: slave select pin a basic example of interconnections between a single master and a single slave is illustrated on figure 33. the mosi pins are connected together as are miso pins. in this way data is transferred serially between master and slave (most significant bit first). when the master device transmits data to a slave device via mosi pin, the slave device responds by sending data to the master device via the miso pin. this implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master de- vice via the sck pin). thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. a status flag is used to indicate that the i/o operation is com- plete. four possible data/clock timing relationships may be chosen (see figure 36) but master and slave must be programmed with the same timing mode. figure 34. serial peripheral interface master/slave 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit vr02131a 57
58/89 ST72121 serial peripheral interface (cont'd) figure 35. serial peripheral interface block diagram dr read buffer 8-bit shift register write read internal bus spi spie spe mstr cpha spr0 spr1 cpol spif wcol modf serial clock generator mosi miso ss sck control state cr sr - - --- it request master control vr02131b spr2 58
59/89 ST72121 serial peripheral interface (cont'd) 4.5.4 functional description figure 33 shows the serial peripheral interface (spi) block diagram. this interface contains 3 dedicated registers: a control register (cr) a status register (sr) a data register (dr) refer to the cr, sr and dr registers insection 4.5.5for the bit definitions. 4.5.4.1 master configuration in a master configuration, the serial clock is gener- ated on the sck pin. procedure select the spr0 & spr1 bits to define the se- rial clock baud rate (see cr register). select the cpol and cpha bits to define one of the four relationships between the data transfer and the serial clock (seefigure 36). the ss pin must be connected to a high level signal during the complete byte transmit se- quence. the mstr and spe bits must be set (they re- main set only if the ss pin is connected to a high level signal). in this configuration the mosi pin is a data output and to the miso pin is a data input. transmit sequence the transmit sequence begins when a byte is writ- ten in the dr register. the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: the spif bit is set by hardware an interrupt is generated if the spie bit is set and the i bit in the ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set 2. a write or a read of the dr register. note: while the spif bit is set, all writes to the dr 59
60/89 ST72121 serial peripheral interface (cont'd) 4.5.4.2 slave configuration in slave configuration, the serial clock is received on the sck pin from the master device. the value of the spr0 & spr1 bits is not used for the data transfer. procedure for correct data transfer, the slave device must be in the same timing mode as the mas- ter device (cpol and cpha bits). seefigure 36. the ss pin must be connected to a low level signal during the complete byte transmit se- quence. clear the mstr bit and set the spe bit to as- sign the pins to alternate function. in this configuration the mosi pin is a data input and the miso pin is a data output. transmit sequence the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: the spif bit is set by hardware an interrupt is generated if spie bit is set and i bit in ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set. 2. a write or a read of the dr register. notes: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 4.5.4.6). depending on the cpha bit, the ss pin has to be set to write to the dr register between each data byte transfer to avoid a write collision (seesection 4.5.4.4). 60
61/89 ST72121 serial peripheral interface (cont'd) 4.5.4.3 data transfer format during an spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). the serial clock is used to syn- chronize the data transfer during a sequence of eight clock pulses. the ss pin allows individual selection of a slave device; the other slave devices that are not select- ed do not interfere with the spi transfer. clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits. the cpol (clock polarity) bit controls the steady state value of the clock when no data is being transferred. this bit affects both master and slave modes. the combination between the cpol and cpha (clock phase) bits selects the data capture clock edge. figure 36, shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. the ss pin is the slave device select input and can be driven by the master device. the master device applies data to its mosi pin- clock edge before the capture clock edge. cpha bit is set the second edge on the sck pin (falling edge if the cpol bit is reset, rising edge if the cpol bit is set) is the msbit capture strobe. data is latched on the occurrence of the first clock transition. no write collision should occur even if the ss pin stays low during a transfer of several bytes (see figure 35). cpha bit is reset the first edge on the sck pin (falling edge if cpol bit is set, rising edge if cpol bit is reset) is the msbit capture strobe. data is latched on the oc- currence of the second clock transition. this pin must be toggled high and low between each byte transmitted (seefigure 35). to protect the transmission from a write collision a low value on the ss pin of a slave device freezes the data in its dr register and does not allow it to be altered. therefore the ss pin must be high to write a new data byte in the dr without producing a write collision. figure 36. cpha / ss timing diagram mosi/miso master ss slave ss (cpha=0) slave ss (cpha=1) byte 1 byte 2 byte 3 vr02131c 61
62/89 ST72121 serial peripheral interface (cont'd) figure 37. data clock timing diagram cpol = 1 cpol = 0 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 cpol = 1 cpol = 0 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) vr02131d 62
63/89 ST72121 serial peripheral interface (cont'd) 4.5.4.4 write collision error a write collision occurs when the software tries to write to the dr register while a data transfer is tak- ing place with an external device. when this hap- pens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. note: a oread collisiono will never occur since the received data byte is placed in a buffer in which access is always synchronous with the mcu oper- ation. in slave mode when the cpha bit is set: the slave device will receive a clock (sck) edge prior to the latch of the first data transfer. this first clock edge will freeze the data in the slave device dr register and output the msbit on to the exter- nal miso pin of the slave device. the ss pin low state enables the slave device but the output of the msbit onto the miso pin does not take place until the first data transfer clock edge. when the cpha bit is reset: data is latched on the occurrence of the first clock transition. the slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the dr register after its ss pin has been pulled low. for this reason, the ss pin must be high, between each data byte transfer, to allow the cpu to write in the dr register without generating a write colli- sion. in master mode collision in the master device is defined as a write of the dr register while the internal serial clock (sck) is in the process of transfer. the ss pin signal must be always high on the master device. wcol bit the wcol bit in the sr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 37). figure 38. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read sr read dr write dr 2nd step spif =0 wcol=0 spif =0 wcol=0 if no transfer has started wcol=1 if a transfer has started clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 before the 2nd step read sr read dr note: writing in dr register in- stead of reading in it do not reset wcol bit read sr or then then then 63
64/89 ST72121 serial peripheral interface (cont'd) 4.5.4.5 master mode fault master mode fault occurs when the master device has its ss pin pulled low, then the modf bit is set. master mode fault affects the spi peripheral in the following ways: the modf bit is set and an spi interrupt is generated if the spie bit is set. the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read or write access to the sr register while the modf bit is set. 2. a write to the cr register. notes: to avoid any multiple slave conflicts in the case of a system comprising several mcus, the ss pin must be pulled high during the clearing se- quence of the modf bit. the spe and mstr bits may be restored to their original state during or af- ter this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device the modf bit can not be set, but in a multi master configuration the device can be in slave mode with this modf bit set. the modf bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine. 4.5.4.6 overrun condition an overrun condition occurs, when the master de- vice has sent several data bytes and the slave de- vice has not cleared the spif bit issuing from the previous data byte transmitted. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the dr register returns this byte. all other bytes are lost. this condition is not detected by the spi peripher- al. 64
65/89 ST72121 serial peripheral interface (cont'd) 4.5.4.7 single master and multimaster configurations there are two types of spi systems: single master system multimaster system single master system a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 38). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written its dr regis- ter. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. multi-master system a multi-master system may also be configured by the user. transfer of master control could be im- plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the cr register and the modf bit in the sr register. figure 39. single master configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu vr02131e 65
66/89 ST72121 serial peripheral interface (cont'd) 4.5.5 register description control register (cr) read/write reset value: 0000xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever spif=1 or modf=1 in the sr register bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss=0 (see section 4.5.4.5 master mode fault). 0: i/o port connected to pins 1: spi alternate functions connected to pins the spe bit is cleared by reset, so the spi periph- eral is not initially connected to the external pins. bit 5 = spr2 divider enable . this bit is set and cleared by software and it is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer totable 17. 0: divider by 2 enabled 1: divider by 2 disabled bit 4 = mstr master. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss=0 (see section 4.5.4.5 master mode fault). 0: slave mode is selected 1: master mode is selected, the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are re- versed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the steady state of the serial clock. the cpol bit affects both the master and slave modes. 0: the steady state is a low value at the sck pin. 1: the steady state is a high value at the sck pin. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. bit 1,0 = spr1 - spr0 serial peripheral rate. these bits are set and cleared by software. used with the spr2 bit, they select one of six baud rates to be used as the serial clock when the device is a master. these 2 bits have no effect in slave mode. table 17. serial peripheral baud rate 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /4 100 f cpu /8 000 f cpu /16 001 f cpu /32 110 f cpu /64 010 f cpu /128 0 1 1 66
67/89 ST72121 serial peripheral interface (cont'd) status register (sr) read only reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag. this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the cr register. it is cleared by a soft- ware sequence (an access to the sr register fol- lowed by a read or write to the dr register). 0: data transfer is in progress or has been ap- proved by a clearing sequence. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is set, all writes to the dr register are inhibited. bit 6 = wcol write collision status. this bit is set by hardware when a write to the dr register is done during a transmit sequence. it is cleared by a software sequence (seefigure 37). 0: no write collision occurred 1: a write collision has been detected bit 5 = unused. bit 4 = modf mode fault flag. this bit is set by hardware when the ss pin is pulled low in master mode (see section 4.5.4.5 master mode fault). an spi interrupt can be gen- erated if spie=1 in the cr register. this bit is cleared by a software sequence (an access to the sr register while modf=1 followed by a write to the cr register). 0: no master mode fault detected 1: a fault in master mode has been detected bits 3-0 = unused. data i/o register (dr) read/write reset value: undefined the dr register is used to transmit and receive data on the serial bus. in the master device only a write to this register will initiate transmission/re- ception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. warning: a write to the dr register places data di- rectly into the shift register for transmission. a read to the dr register returns the value located in the buffer and not the contents of the shift regis- ter (see figure 34). 70 spif wcol - modf - - - - 70 d7 d6 d5 d4 d3 d2 d1 d0 67
68/89 ST72121 serial peripheral interface (cont'd) table 18. spi register map and reset values address (hex.) register name 76543210 21 dr reset value d7 x d6 x d5 x d4 x d3 x d2 x d1 x d0 x 22 cr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 23 sr reset value spif 0 wcol 0 - 0 modf 0 - 0 - 0 - 0 - 0 68
69/89 ST72121 5 instruction set 5.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 19. st7 addressing mode overview note 1. at the time the instruction is executed, the program counter (pc) points to the instruction follow- ing jrxx. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination/ source pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc-128/pc+127 1) +1 relative indirect jrne [$10] pc-128/pc+127 1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 69
70/89 ST72121 st7 addressing modes (cont'd) 5.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 5.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the the operand value. . 5.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 5.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 5.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations 70
71/89 ST72121 st7 addressing modes (cont'd) 5.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 20. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 5.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtrac- tion operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/ indirect instructions function jrxx conditional jump callr call relative 71
72/89 ST72121 5.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four bytes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the ef- fective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a y one. pix 92 replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed ad- dressing mode to an instruction using indirect x in- dexed addressing mode. piy 91 replace an instruction using x in- direct indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret code condition flag modification sim rim scf rcf 72
73/89 ST72121 instruction groups (cont'd) mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > 73
74/89 ST72121 instruction groups (cont'd) mnemo description function/example dst src h i n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z 74
75/89 ST72121 6 electrical characteristics 6.1 absolute maximum ratings this product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. for proper operation it is recommended that v i and v o be higher than v ss and lower than v dd . reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (v dd or v ss ). power considerations .the average chip-junc- tion temperature, t j , in celsius can be obtained from: t j = ta + pd x rthja where: t a = ambient temperature. rthja = package thermal resistance (junction-to ambient). p d =p int +p port . p int =i dd xv dd (chip internal power). p port =port power dissipation determined by the user) note: stresses above those listed as aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. symbol parameter value unit v dd digital supply voltage -0.3 to 6.0 v v dda analog supply and reference voltage v dd - 0.3 to v dd + 0.3 v v i input voltage v ss - 0.3 to v dd + 0.3 v v ai analog input voltage (a/d converter) v ss - 0.3 to v dd + 0.3 v ssa -0.3 to v dda +0.3 v v o output voltage v ss - 0.3 to v dd + 0.3 v iv dd total current into v dd (source) 100 ma iv ss total current out of v ss (sink) 100 ma t j junction temperature 150 c t stg storage temperature -60 to 150 c 75
76/89 ST72121 6.2 recommended operating conditions note 1) a safe reset (with low voltage detector option) is not guaranteed at 16 mhz. 2) a/d operation and oscillator start-up are not guaranteed below 1mhz. figure 40. maximum operating frequency (f max ) versus supply voltage (v dd ) note: the shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions. symbol parameter test conditi ons value unit min. typ. max. t a operating temperature 1 suffix version 0 70 c 6 suffix version -40 85 v dd operating supply voltage f osc = 16 mhz, f cpu = 8 mhz f osc = 8 mhz, f cpu = 4 mhz 3.5 1) 3.0 6.0 6.0 v f osc oscillator frequency v dd = 3.0v v dd = 3.5v 0 2) 0 2) 8 16 mhz 2.5 3 3.5 4 4.5 5 5.5 6 supply voltage (vdd) maximum 16 8 frequency (mhz) functionality is not guaranteed in this area 76
77/89 ST72121 6.3 dc electrical characteristics (t a =-40 cto+85 c and v dd = 5v unless otherwise specified) notes: 1. hysteresis voltage between switching levels. based on characterisation results, not tested. 2. cpu running with memory access, no dc load or activity on i/o's; clock input (oscin) driven by external square wave. 3. no dc load or activity on i/o's; clock input (oscin) driven by external square wave. 4. except oscin and oscout 5. wait mode with slow mode selected. based on characterisation results, not tested. symbol parameter test cond itions value unit min. typ. max. v il input low level voltage all input pins 3v < v dd <6v v dd x 0.3 v v ih input high level voltage all input pins 3v < v dd <6v v dd x 0.7 v v hys hysteresis voltage 1) all input pins 400 mv v ol low level output voltage all output pins i ol =+10 m a i ol = + 2ma 0.1 0.4 v low level output voltage high sink i/o pins i ol =+10 m a i ol = +10ma i ol = + 20ma 0.1 1.5 3.0 v oh high level output voltage all output pins i oh =-10 m a i oh =-2ma 4.9 4.2 v i il i ih input leakage current all input pins but reset 4) v in =v ss (no pull-up configured) v in =v dd 0.1 1.0 m a i ih input leakage current reset pin v in =v dd 0.1 1.0 r on reset weak pull-up r on v in >v ih v in 78/89 ST72121 6.4 oscillator characteristics (t a =-40 cto+85 c unless otherwise specified) 6.5 peripheral characteristics notes: 1. the safe reset cannot be guaranted by the lvd when fosc is greater than 8mhz. 2. based on characterisation results, not tested. symbol parameter test conditions value unit min. typ. max. g m oscillator transconductance 2 9 ma/v f osc crystal frequency 1 16 mhz t start osc. start up time v dd =5v 10% 50 ms low voltage detection reset electrical specifications (optio n) symbol parameter conditions min. typ. max. unit v lvdup lvd reset trigger, v dd rising edge f osc = 8 mhz max 1) . 4.1 v v lvddown lvd reset trigger, v dd falling edge 3.35 3.85 v v lvdhys lvd reset trigger, hysteresis 2) 250 mv 78
79/89 ST72121 peripheral characteristics (cont'd) serial peripheral interface ref. characteristics configu ration symbol value unit min. max. spi frequency master f spi (m) f cpu slave f spi (s) dc f cpu 1 cycle time master t cyc(m) 4 500 cc ns slave t cyc(s) 2 250 cc ns 2 enable lead time master t lead(m) ns slave t lead(s) 120 ns 3 enable lag time master ns slave 120 ns 4 clock (sck)high time master t w(sckh) 100 ns slave t w(sckh) 90 ns 5 clock (sck) low time master t w(sckl) 100 ns slave t w(sckl) 90 ns 6 data set-up time master t su(m) 100 ns slave t su(s) 100 ns 7 data hold time (inputs) master t h(m) 100 ns slave t h(s) 100 ns 8 access time (time to data active from high impedance state) slave t a 0 120 ns 9 disable time (hold time to high im- pedance state) slave t dis 240 ns 10 data valid master (before capture edge) t v(m) 0.25 t cyc(m) slave (after enable edge) t v(s) 120 ns 11 data hold time (outputs) master (before capture edge) t ho(m) 0.25 t cyc(m) slave (after enable edge) t ho(s) 0ns 12 rise time (20% v dd to 70% v dd , c l = 200pf) spi outputs (sck, mosi, miso) t rm 100 ns spi inputs (sck, mosi, mi- so, ss) t rs 2.0 m s 13 fall time (70% v dd to 20% v dd ,c l = 200pf) spi outputs (sck, mosi, miso) t fm 100 ns spi inputs (sck, mosi, mi- so, ss) t fs 2.0 m s 1 128 --------- - 1 4 -- - 1 2 -- - 79
80/89 ST72121 peripheral characteristics (cont'd) figure 41. spi master timing diagram cpol=0, cpha=1 note : measurement points are v ol ,v oh ,v il and v ih figure 42. spi master timing diagram cpol=1, cpha=1 note : measurement points are v ol ,v oh ,v il and v ih 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 5 4 vr000107 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr000108 d7-out d6-out d0-out d7-in d6-in d0-in 80
81/89 ST72121 peripheral characteristics (cont'd) figure 43. spi master timing diagram cpol=0, cpha=0 note : measurement points are v ol ,v oh ,v il and v ih figure 44. spi master timing diagram cpol=1, cpha=0 note : measurement points are v ol ,v oh ,v il and v ih 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr 000109 d7-out d6-out d0-out d7-in d6-in d0-in 1 67 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr000110 d7-out d6-out d0-out d7-in d6-in d0-in 81
82/89 ST72121 peripheral characteristics (cont'd) figure 45. spi slave timing diagram cpol=0, cpha=1 note: measurement points are v ol ,v oh ,v il and v ih figure 46. spi slave timing diagram cpol=1, cpha=1 note: measurement points are v ol ,v oh ,v il and v ih 1 67 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000111 d7-out d6-out d0-out d7-in d6-in d0-in 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 54 (input) 2 3 8 9 high-z vr000112 d7-out d6-out d0-out d7-in d6-in d0-in 82
83/89 ST72121 peripheral characteristics (cont'd) figure 47. spi slave timing diagram cpol=0, cpha=0 figure 48. spi slave timing diagram cpol=1, cpha=0 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000113 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000114 d7-in d6-in d0-in d7-out d6-out d0-out 83
84/89 ST72121 7 general information 7.1 eprom erasure eprom version devices are erased by exposure to high intensity uv light admitted through the transparent window. this exposure discharges the floating gate to its initial state through induced photo current. it is recommended that the eprom devices be kept out of direct sunlight, since the uv content of sunlight can be sufficient to cause functional fail- ure. extended exposure to room level fluorescent lighting may also cause erasure. an opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting con- ditions. covering the window also reduces i dd in power-saving modes due to photo-diode leakage currents. an ultraviolet source of wave length 2537 ? yield- ing a total integrated dosage of 15 watt-sec/cm 2 is required to erase the device. it will be erased in 15 to 20 minutes if such a uv lamp with a 12mw/cm 2 power rating is placed 1 inch from the device win- dow without any interposed filters. 84
85/89 ST72121 7.2 package mechanical data figure 49. 42-pin shrink plastic dual in-line package, 600-mil width figure 50. 42-pin shrink ceramic dual in-line package, 600-mil width dim. mm inches min typ max min typ max a 5.08 0.200 a1 0.51 0.020 a2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.46 0.56 0.018 0.022 b2 1.02 1.14 0.040 0.045 c 0.23 0.25 0.38 0.009 0.010 0.015 d 36.58 36.83 37.08 1.440 1.450 1.460 e 15.24 16.00 0.600 0.630 e1 12.70 13.72 14.48 0.500 0.540 0.570 e 1.78 0.070 ea 15.24 0.600 eb 18.54 0.730 ec 1.52 0.000 0.060 l 2.54 3.30 3.56 0.100 0.130 0.140 number of pins n42 pdip42s dim. mm inches min typ max min typ max a 4.01 0.158 a1 0.76 0.030 b 0.38 0.46 0.56 0.015 0.018 0.022 b1 0.76 0.89 1.02 0.030 0.035 0.040 c 0.23 0.25 0.38 0.009 0.010 0.015 d 36.68 37.34 38.00 1.444 1.470 1.496 d1 35.56 1.400 e1 14.48 14.99 15.49 0.570 0.590 0.610 e 1.78 0.070 g 14.12 14.38 14.63 0.556 0.566 0.576 g1 18.69 18.95 19.20 0.736 0.746 0.756 g2 1.14 0.045 g3 11.05 11.30 11.56 0.435 0.445 0.455 g4 15.11 15.37 15.62 0.595 0.605 0.615 l 2.92 5.08 0.115 0.200 s 0.89 0.035 number of pins n42 cdip42sw 85
86/89 ST72121 figure 51. 44-pin thin quad flat package dim mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 d3 8.00 0.315 e 12.00 0.472 e1 10.00 0.394 e3 8.00 0.315 e 0.80 0.031 k 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 44 b c l1 l k 86
87/89 ST72121 7.3 ordering information each device is available for production in user pro- grammable version (otp) as well as in factory coded version (rom). otp devices are shipped to customer with a default blank content ffh, while rom factory coded parts contain the code sent by customer. there is one common eprom version for debugging and prototyping which features the maximum memory size and peripherals of the family. care must be taken to only use resources available on the target device. 7.3.1 transfer of customer code customer code is made up of the rom contents and the list of the selected options (if any). the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file gener- ated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmi- croelectronics using the correctly completed op- tion list appended. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. figure 52. rom factory coded device types figure 53. otp user programmable device types note: the st72e121j4d0 (cerdip 25 c) is used as the eprom versions for the above devices. device package temp. range xxx / code name (defined by stmicroelectronics) 1= standard 0 to +70 c 6= industrial -40 to +85 c b= plastic dip t= plastic tqfp ST72121j2 ST72121j4 device package temp. range s= lvd reset option 6= industrial -40 to +85 c b= plastic dip t= plastic tqfp st72t121j2 st72t121j4 x 87
88/89 ST72121 ST72121 microcontroller option list customer ............................. address ............................. ............................. contact ............................. phone no ............................. reference ............................. stmicroelectronics references device: [ ] ST72121j2 [ ] ST72121j4 option: [ ] software watchdog [ ] hardware watchdog [ ] low voltage detector reset package: [ ] dual in-line plastic[ ] thin quad flat pack: [ ] standard (stick) [ ] tape & reel temperature range: [ ] 0 cto+70 c[]-40 cto+85 c special marking: [ ] no [ ] yes o_ _ _ _ _ _ _ _ _ _ _ o authorized characters are letters, digits, '.', '-', '/' and spaces only. maximum character count: sdip42: 16 tqfp44: 10 comments : supply operating range in the application: oscillator frequency in the application: notes ............................. signature ............................. date ............................. 88
89/89 ST72121 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http:/ /www.st.com 89

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